HYSTSEL=HYST0, WARMTIME=4CYCLES
Control Register
| EN | Analog Comparator Enable  |  
| MUXEN | Input Mux Enable  |  
| INACTVAL | Inactive Value  |  
| GPIOINV | Comparator GPIO Output Invert  |  
| HYSTSEL | Hysteresis Select 0 (HYST0): No hysteresis. 1 (HYST1): ~15 mV hysteresis. 2 (HYST2): ~22 mV hysteresis. 3 (HYST3): ~29 mV hysteresis. 4 (HYST4): ~36 mV hysteresis. 5 (HYST5): ~43 mV hysteresis. 6 (HYST6): ~50 mV hysteresis. 7 (HYST7): ~57 mV hysteresis.  |  
| WARMTIME | Warm-up Time 0 (4CYCLES): 4 HFPERCLK cycles. 1 (8CYCLES): 8 HFPERCLK cycles. 2 (16CYCLES): 16 HFPERCLK cycles. 3 (32CYCLES): 32 HFPERCLK cycles. 4 (64CYCLES): 64 HFPERCLK cycles. 5 (128CYCLES): 128 HFPERCLK cycles. 6 (256CYCLES): 256 HFPERCLK cycles. 7 (512CYCLES): 512 HFPERCLK cycles.  |  
| IRISE | Rising Edge Interrupt Sense  |  
| IFALL | Falling Edge Interrupt Sense  |  
| BIASPROG | Bias Configuration  |  
| HALFBIAS | Half Bias Current  |  
| FULLBIAS | Full Bias Current  |